1. Field of the Invention
The present invention relates to a thermoelectric conversion module and a method for manufacturing the thermoelectric conversion module, and more particularly, to an improvement in a method for manufacturing a compact, high-performance thermoelectric conversion module.
2. Description of the Related Art
Conventional techniques relating to the present invention are disclosed in Japanese Unexamined Patent Application Publication No. 8-153899 and Japanese Unexamined Patent Application Publication No. 8-222770.
Japanese Unexamined Patent Application Publication No. 8-153899 discloses a thermoelectric conversion module including an insulating frame having a plurality of through-holes spaced from each other. The through-holes contain p-type or n-type compound semiconductor elements. The through-holes containing the p-type compound semiconductor elements and the through-holes containing the n-type compound semiconductor elements are alternately arranged. Electrodes are arranged on the upper and lower surfaces of the frame so as to electrically connect pairs of the p-type and n-type compound semiconductor elements to each other in series. As disclosed in Japanese Unexamined Patent Application Publication No. 8-153899, the frame is made of glass or ceramic.
In the thermoelectric conversion module disclosed in Japanese Unexamined Patent Application Publication No. 8-153899, the p-type and n-type compound semiconductor elements are each made of one type of compound semiconductor material. That is, one through-hole contains one type of compound semiconductor material. Therefore, the thermoelectric figure of merit of each element peaks at one temperature, that is, the element has a single conversion peak. Thus, the element has relatively low thermoelectric conversion efficiency.
Japanese Unexamined Patent Application Publication No. 8-222770 discloses a method for manufacturing a thermoelectric conversion module. The method includes a step of preparing n-type laminates such that tabular n-type thermoelectric semiconductors and tabular insulators are alternately stacked and the stack is cut substantially perpendicularly to the lamination plane, a step of preparing p-type laminates such that tabular p-type thermoelectric semiconductors and tabular insulators are alternately stacked and the stack is cut substantially perpendicularly to the lamination plane, a step of alternately stacking the n-type laminates and the p-type laminates such that the insulators are sandwiched between the n-type and p-type laminates, and a step of forming wiring conductors connecting the n-type thermoelectric semiconductors to the p-type thermoelectric semiconductors adjacent thereto in series. As disclosed in Japanese Unexamined Patent Application Publication No. 8-222770, the insulators are made of an epoxy resin.
According to the method disclosed in Japanese Unexamined Patent Application Publication No. 8-222770, the n-type and p-type laminates are likely to be misaligned with each other in the step of alternately stacking the n-type and p-type laminates. This prevents the thermoelectric semiconductors and the wiring conductors from being properly electrically connected to each other. Therefore, the thermoelectric semiconductors and the wiring conductors may be electrically disconnected from each other or short-circuited.